1. Technical Field of the Invention
The present invention relates in general to the communications signal processing field and, in particular, to an improved phase digitizer and method for use in the radio communications field.
2. Description of Related Art
In many electronic signal processing applications, it would be highly advantageous if the instantaneous phase of an alternating current (AC) signal were to be made directly available in a digital format. For example, it would be especially useful to have a digital representation of a signal available if it is to be numerically processed.
A significant problem encountered with existing phase-to-digital signal conversion approaches is that the phase of a signal with a fixed frequency is a continuous ramp, and to digitally represent such a ramp ultimately can entail the use of an infinite number of bits. An existing solution to this problem is to represent the phase of the signal in a circular domain such as modulo 2.pi.. For example, if an 8-bit word is chosen to represent the phase of a signal, then the circular phase angle, 0 . . . 2.pi., can be mapped to match the circular domain, or Galois field, of the binary word, 0.256 (modulo 256). This mapping of one circular domain onto another greatly simplifies existing numerical processing approaches.
FIG. 1 is a schematic block diagram of an existing phase digitizer circuit, which is used to convert a signal phase to a digital signal. However, before discussing any of the details shown in FIG. 1, at this point it will be useful to describe the design of a typical phase-to-digital signal conversion circuit. Assume that a reference clock signal can be generated, which is an integer multiple (e.g., binary) of an input signal frequency. The reference clock signal is input to a digital counter, which functions to divide by the integer multiple so that the divider count cycle repeats at the same rate as the expected signal input frequency. Consequently, the state of the counter can be visualized as a phase vector, which rotates precisely one revolution for each unmodulated input signal period. An output value can be produced by recording the state of the counter when the input signal passes through zero ("zero crossing"). The counter state recording can be initiated by a trigger which results from the occurrence of two events: (1) a sample pulse is generated which indicates that a measurement is desired; and (2) zero crossing of the input signal. Those values recorded for negative zero crossings are 180 degrees out of phase with those values recorded for positive zero crossings. These out of phase values can be compensated for by adding or subtracting 180 degrees from the values recorded for negative zero crossings. Adding 180 degrees to a recorded value yields the same result as subtracting 180 degrees because of the wrap-around effects of the circular phase domain.
Applying these principles to the phase digitizer circuitry 10 shown in FIG. 1, a reference clock signal is input to a digital reference generator 12, which outputs a corresponding digital reference signal. A sample of the signal desired to be digitized is input to a trigger circuit 16, which loads the value (i.e., phase) of the digital reference signal into a register 14 at the input signal zero crossing point which is nearest to the desired sample. The output of register 14 is a digital word representing the phase of the desired sample. If the value loaded by the trigger is based on a negative zero crossing, a negative zero crossing compensation circuit 18 adds (or subtracts) 180 degrees to the digital word from register 14. A second register (optional) 20 can be used to synchronize the output samples to the input pulse samples. Certain refinements have been made to the digitizer shown in FIG. 1, but the principles of operation still remain the same.
The primary drawback of the phase digitizer shown in and described with respect to FIG. 1 is that, as discussed above, the phase recordings occur at the zero crossings of the input signals. As such, for most applications, it would be preferable to generate output samples at a constant rate not so related to the input signal. The trigger circuit can be designed to accommodate this feature by triggering all phase recordings at the zero crossings nearest to the desired samples. Unfortunately, this accommodation introduces an error, which results from a difference between the point in time when the phase was sampled and the point in time that the sample was desired. Assuming that a phase sample can be recorded for both positive and negative zero crossings, this difference or error should not be greater than T/4, where T is the input signal period. However, the magnitude of the phase error caused by this time difference depends on the frequency deviation of the signal. For example, as illustrated by FIG. 2, two different input signals (e.g., one at 100 kHz, the other at 1 MHz, both with .+-.10 kHz maximum frequency deviation) will have a respective maximum phase error of: (1).phi..sub.error (100 kHz)=1/4(100e.sup.3 -10e.sup.3).sup.-1 *10e.sup.3 *360=10 degrees; and (2).phi..sub.error (1 MHz)=1/4(1e.sup.6 -10e.sup.3).sup.-1 *10e.sup.3 *360=0.91 degrees.
For some applications, this amount of phase error is not a significant problem. However, this error becomes more significant in those applications having a relatively large signal deviation-to-signal frequency (deviation-to-frequency) ratio. Notably, as an input signal's deviation-to-frequency ratio increases, the phase digitizer's performance appreciably degrades. In order to improve the performance of applications with large deviation-to-frequency ratios, an existing error compensation approach is to record two or more phase measurements and their relationship in time relative to the desired sample. The results can then be interpolated (or extrapolated) to derive an estimated value for the sample.
For example, FIG. 3 is a diagram that illustrates such an error compensation approach. Referring to FIG. 3, an interpolated output sample, s (i.e., involving numeric operations associated with the signal phase performed as modulo 2.pi.) can be derived from the two recorded phase measurements, p1 and p2, by the expression: s=p1+(p2-p1)*t1/(t1+t2). Notably, these numeric operations are performed with a digital processor as modulo 2.pi. relatively easily by ignoring any overflow and allowing the results to "wrap around" in that circular domain. However, the hardware "costs" (e.g., size and power consumption) associated with such an interpolation approach are relatively high, because some type of device (typically one or more binary counters) is typically utilized to measure the time between the recorded phases and the desired sample, and other hardware devices also are utilized to perform related division and multiplication functions. These hardware "costs" can be diminished slightly by using a "look up table" to replace some of the multiplication, division, and other arithmetic operations involved. However, these "costs" still remain significantly large. As described below, the present invention successfully resolves these problems.